FIGS. 5(a)-5(e) illustrate a method for forming a GaAs epitaxial wafer having a cleavage plane orientation flat. In these figures, reference numeral 1 designates a GaAs monocrystalline ingot. This GaAs monocrystalline ingot 1 is formed by a boat grown method in which GaAs is melted in an electric furnace and a crystalline seed is moved from a high temperature region to a low temperature region in the furnace to grow the GaAs ingot with the crystalline seed as a core, Alternatively, it may be formed by a pull method in which GaAs is melted in a crucible and the melted GaAs is slowly pulled up by a seed crystal bar, Reference numeral 2 designates a cylindrical GaAs monocrystalline ingot made of the GaAs monocrystalline ingot 1. Reference numeral 3 designates a GaAs wafer obtained by slicing the cylindrical GaAs monocrystalline ingot 3 in a prescribed thickness. Reference numeral 4 designates a GaAs wafer having an orientation flat 4a formed by cleaving a portion of the GaAs wafer 3 along a cleavage plane. Generally, the orientation flat 4a is formed at a position relating to a crystal orientation of the GaAs substrate 3 and serves as a mark when the orientation of the wafer is detected in a subsequent process. Reference numeral 5 designates a GaAs epitaxial wafer in which an epitaxial layer 51 has been grown on the GaAs wafer 4.
A description is given of the production process. Initially, as illustrated in FIG. 5(a), a high quality GaAs monocrystalline ingot 1 is formed by the above-described boat grown method or the pull method. Then, as illustrated in FIG. 5(b), opposite end portions of the ingot 1 are cut off to remove deformed portions of the ingot 1. Then, the ingot 1 is formed into a cylindrical shape by polishing its periphery, whereby a diameter of a wafer to be formed is determined. Preferably, the diameter is a few inches.
Thereafter, the cylindrical GaAs monocrystalline ingot 2 is sliced using a very thin diamond blade, providing a GaAs wafer 3 shown in FIG. 5(c). When the diameter of the wafer is 2 inches, it is sliced in a thickness of about 400 microns. When the diameter is 3 inches, it is sliced in a thickness of about 600 microns.
Then, as illustrated in FIG. 5(d), an end portion of the GaAs wafer 3 is cleaved along a cleavage plane to form an orientation flat 4a. Since there are differences in thicknesses of a plurality of GaAs wafers 4 with the orientation flat 4a due to the slicing process, both surfaces of the GaAs wafers 4 are lapped in a solution comprising aluminium oxide and glycerine or the like while applying pressure thereto, whereby the thicknesses of the GaAs wafers 4 are made even. Then, a damaged layer and a contaminated layer each about 10 microns thick on the surface and the periphery of the wafer 4 due to the lapping are removed by etching. Then, abrasive is dropped onto the wafer and the wafer is polished using a porous pad or the like to improve the flatness of the wafer, resulting in a mirrorlike surface of the GaAs wafer 4.
Thereafter, as illustrated in FIG. 5(e), an epitaxial layer 51 is grown on the surface of the GaAs wafer 4 by MOCVD or the like, resulting in a GaAs epitaxial wafer 5 with the cleavage plane serving as the orientation flat.
FIGS. 6(a)-6(e) illustrate another conventional method for producing the GaAs epitaxial wafer with the cleavage plane as the orientation flat. In this method, after directly slicing a GaAs monocrystalline ingot, a prescribed diameter of a wafer to be formed is obtained by stamping and then an orientation flat is formed. In FIGS. 6(a)-6(e), reference numeral 6 designates a GaAs wafer for stamping obtained by directly slicing the GaAs monocrystalline ingot 1.
Initially, as illustrated in FIG. 6(a), a GaAs monocrystalline ingot 1 is formed by the boat grown method, the pull method, or the like. Then, the ingot 1 is sliced in a prescribed thickness, providing a GaAs wafer 6 shown in FIG. 6(b).
Then, as illustrated in FIG. 6(c), a GaAs wafer 3 is stamped out from the GaAs wafer 6 using a trimming die (not shown) having a diameter equal to a desired diameter of a wafer to be formed.
Then, as illustrated in FIG. 6(d), an end portion of the GaAs wafer 3 is cleaved along a cleavage plane to form an orientation flat 4a. Thereafter, lapping, etching, and polishing processes are applied to the GaAs wafer 4 with the orientation flat 4a to provide a mirrorlike surface of the GaAs wafer 4.
Then, as illustrated in FIG. 6(e), an epitaxial layer 51 is grown on the GaAs wafer 4 by MOCVD or the like, resulting in a GaAs epitaxial wafer 5 with the cleavage plane as the orientation flat.
In the above-described conventional methods, since the orientation flat is produced by cleaving the wafer along the cleavage plane, the orientation flat is produced with high precision. However, since the surface treatment like the polishing is performed after the formation of the orientation flat 4a edges of the cleavage plane of the orientation flat are rounded as shown in FIG. 7. In addition, when the epitaxial layer 51 is grown on the wafer 4, the edges of the cleavage plane of the orientation flat 4a are also rounded due to the grown epitaxial layer 51. Therefore, when a position of the GaAs epitaxial wafer 5 is detected on the basis of the orientation flat 4athe , precision of the position detection is lowered.
In addition, when the orientation flat 4a is formed by cleaving the GaAs wafer 4, the GaAs wafer 4 is unfavorably cracked or broken, resulting in a poor production yield.